The present invention relates to a method of manufacturing a semiconductor device exhibiting reduced capacitance loading, improved electromigration resistance and increased reliability. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices comprising sub-micron dimensions having low resistance vias and exhibiting rapid circuit speed.
As integrated circuit geometries continue to plunge deeper into the sub-micron regime, it becomes increasingly difficult to satisfy the demands for dimensional accuracy. Moreover, interconnection technology is constantly challenged to satisfy the ever increasing requirements for high performance associated with ultra large scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit speed. As integrated circuits become complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting factor in fabrication.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
A conductive plug filling a via bole is typically formed by depositing an interlayer dielectric (ILD) on a metal level comprising at least one metal feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. The excess conductive material or overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD, such as a trench or via hole, and filling the opening with a metal to form a metal line or via, respectively. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, and filling the opening with a conductive material, typically a metal, to simultaneously form a lower contact or via in contact with an upper conductive line.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-a-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein a dielectric layer, e.g., interlayer dielectric, is formed over a patterned underlying metal level having a capping layer thereon, e.g., Cu or Cu alloy features with a silicon nitride capping layer. An opening is formed in the dielectric layer. A barrier layer and optional seedlayer are then sequentially deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an interlayer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8.0 for deposited silicon nitride. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9, based upon a value of the dielectric constant of a vacuum as one (1). One type of low-k material that has been explored are a group of spin on or CVD siloxane materials, such as hydrogen silsesquioxane (HSQ) and methyl silsequioxane (MSQ) and BLACK-DIAMOND(trademark) dielectric available for Applied Materials, Santa Clara, Calif. and silicon-carbon-oxygen-hydrogen (SiCOH) organic dielectrics. There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which offer promise for use as an ILD, such as FLARE 20(trademark) dielectric, a poly(arylene) ether, available from Allied Signal, Advanced Micromechanic Materials, Sunnyvale, Calif. BCB (divinylsiloxane bis-benzocyclobutene) and SILK(trademark) dielectric, an organic polymer similar to BCB, both available from Dow Chemical Co., Mildland, Mich.
In implementing Cu and/or Cu alloy damascene techniques to form interconnection patterns with dimensions in the deep sub-micron regime, particularly when employing various low-k materials, including porous oxides, such as dielectric oxides having a porosity of about 30% to about 80% and a dielectric constant (k) of about 2.0 or lower, various problems evolve which degrade the resulting semiconductor device. For example, copper readily diffuses into conventional silicon-based materials such as polysilicon, single-crystalline silicon, silicon dioxide, and low-k inorganic and organic materials. Once semiconductive silicon-based materials are Cu doped, transistors made within or in close proximity to the Cu doped silicon-based regions either cease to function properly or are significantly degraded in electrical performance.
Several dielectric materials have evolved which contain halogens, such as fluorine (F), e.g., F-doped silicon dioxide derived from tetraethyl orthosilicate (F-TEOS) and F-doped silicate glass (FSG). In implementing conventional damascene techniques with Cu, it was found that the barrier layer initially deposited to line the opening does not adhere well to the dielectric layer, particularly F-containing low-k ILDs such as F-TEOS and FSG. Such an adhesion problems adversely impact electromigration resistance and device reliability.
Additional problems attendant upon implementing Cu or Cu alloy interconnect technology stem from the difficulty in removing a thin copper oxide film formed on the upper surface of the lower Cu or Cu alloy metal feature by chemical mechanical polishing (CMP), leading to voids, electromigration problems and increasing vias resistance. Another source of via resistance stems from the presence of polymers or polymeric deposits generated by anisotropic etching to form the opening in the dielectric layer.
In addition, conventional practices employ an argon (Ar) sputter etching technique to round the corners of the opening to facilitate filling, to remove surface oxides from the underlying metal feature and to remove residual contamination. However, such Ar sputter etching typically removes a portion of the upper surface of the lower Cu or Cu alloy feature which redeposits on the side surfaces of the dielectric layer defining the opening formed therein. The resulting structure would contain Cu between the subsequently deposited barrier metal and dielectric layer which ultimately penetrates the dielectric layer and eventually poisons one or more transistors of the device.
Accordingly, there exists a need for efficient methodology enabling the formation of interconnection structures containing low resistance vias. There exists a particular need for efficient methodology enabling the formation of low resistance Cu or Cu alloy interconnection structures exhibiting high reliability and high electromigration resistance.
An advantage of the present invention is a method of manufacturing a semiconductor device having low resistance vias.
Another advantage of the present invention is a method of manufacturing a semiconductor device with Cu and/or Cu alloy interconnection patterns in low-k dielectric layers exhibiting reduced parasitic RC time delays, improved electromigration resistance, reduced via resistance and increased device reliability.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer exposing an upper surface of a lower metal feature; and sequentially treating the opening and upper surface of the lower metal feature with: (a) a plasma containing ammonia (NH3); following by (b) a plasma containing nitrogen (N2) and hydrogen (H2).
Embodiments of the present invention comprise forming a dual damascene opening in an interlayer dielectric comprising a dielectric material having a dielectric constant less than about 3.9, the opening exposing an upper surface of a lower Cu feature, sequentially treating the opening and upper surface of the lower Cu feature with an NH3 plasma followed by an N2/H2 plasma. Subsequently, a barrier layer is deposited lining the opening, a seedlayer deposited thereon, and the opening filled with Cu followed by CMP and deposition of a capping layer, such as silicon nitride or silicon carbide. Embodiments of the present invention further include the use of low-k dielectric materials, such as F-TEOS, SLCOH and BLACK-DIAMOND(trademark) dielectric. As used throughout this disclosure, the symbol xe2x80x9cCuxe2x80x9d is intended to include substantially pure elemental copper, copper containing unavoidable impurities and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zironcium.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded and illustrative in nature, and not as restrictive.